To mention just one application area, wireless mobile product technology continues to demand more applications performance, less power drain on batteries, and lower integrated circuit cost of manufacture. These demands translate into metrics such as milliwatts of power dissipation per gigahertz (mW/GHz), trillions of operations (GigaOPS or GOPS) per second or per square centimeter (GOPS/cm2), battery life (days), and so on. Improvements in processes of manufacture and improvements in integrated circuit structure can make improved wireless mobile products possible. Continuing trends in semiconductor product manufacturing include reduction in electrical device feature sizes (scaling). However, currently, the prospect of smaller processes below 0.09 micron (90 nanometers) gate width suggests problems such as 1) increased leakage current that impedes the goal of reduced power dissipation and 2) increased resistances in signal paths that introduce undesirable signal delay that impedes the goal of higher speed and GOPS.
Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. In metal-oxide-semiconductor field-effect transistors (MOSFETs), a gate electrode is energized to create an electric field in a channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel. A gate dielectric or gate oxide is formed over the channel, and a gate electrode is formed over the gate dielectric. Together, the gate dielectric and gate electrode form what is called the gate stack, which is patterned and etched to form the gate structure overlying the channel region of the substrate.
In the MOS transistor, the gate requires a threshold voltage (Vt) to render the channel conductive. Complementary MOS (CMOS) processes fabricate both n-channel and p-channel (NMOS and PMOS) transistors to make logic and other circuitry. For enhancement-mode (normally off) devices, the threshold voltage Vt is positive for NMOS and the threshold voltage is negative for PMOS transistors. The threshold voltage is influenced by what is called the work function difference.
The work function of one material is the difference between the reference level of the vacuum and an energy level called the Fermi level or thermodynamic equilibrium level attributed by solid state physics to the material. When the material is a semiconductor, allowed energies of carriers remarkably are divided into ranges, a lower one called the valence band and a higher one called the conduction band separated by a bandgap of unused range of energies between those two bands. Undoped semiconductor material, called intrinsic semiconductor, has a Fermi level in the middle of the bandgap.
Generally speaking, the work function is a measure of the energy, in electron volts (eV), required to eject an electron in the material outside of a material atom to the vacuum, if the electron were initially at the Fermi level. The work function difference between the gate and the channel is essentially an arithmetic difference between the work function of the gate material closest to the channel region and the work function of the material of the channel region. N-doping moves the Fermi level higher toward the conduction band edge and reduces the work function relative to the work function of intrinsic semiconductor. P-doping moves the Fermi level lower toward the valence band edge and increases the work function relative to the work function of intrinsic semiconductor.
Generally, a desirable process of manufacture makes the threshold voltages (Vt) for the NMOS and PMOS transistors predictable, repeatable, and stable. To establish Vt values, the work function differences of the respective PMOS and NMOS gate materials and their corresponding channel regions are independently established through channel processing and gate processing.
Channel processing can include shallow dopant (impurity) implants to the prospective channel regions of the semiconductor body, sometimes referred to as threshold adjust (Vt adjust) implants. These implanted impurities introduce a sheet of fixed charge located under the gate oxide. A Vt adjust implant for the NMOS devices introduces boron or other p-type impurities into the NMOS channel region to raise the channel work function (sometimes referred to as a VTN implant). A Vt adjust implant for the PMOS devices introduces arsenic, phosphorus, or other n-type impurities to lower the PMOS channel work function (VTP implant). In this manner, the Vt for the channels can be separately adjusted for NMOS and PMOS devices. Channel processing may include multiple implants, for example, a Vt adjust implant, a punch-thru implant to suppress punch-through, and a channel stop implant, for each of the NMOS and PMOS devices.
Gate processing adjusts the work function of the gate materials for PMOS and NMOS independently. Polysilicon has a work function that is readily raised or lowered by doping the polysilicon with p-type or n-type impurities for PMOS and NMOS respectively, typically during implantation of the respective source/drain regions following gate patterning. In this way, the final gate work functions are typically near the Si conduction band edge for NMOS and near the valence band edge for PMOS. (The semiconductor has permitted bands of energy levels for electrons;. The bands are separated by a bandgap of energies in which electrons can not exist. In undoped semiconductor the Fermi level is at the middle of the bandgap, and doping moves the Fermi level closer to, or even into one band or the other.)
Dopants in the polysilicon also increase the electrical conductivity of the gate. Polysilicon has thus far been widely using in the fabrication of CMOS devices, wherein the gate doping provides a desired gate contact conductivity, and the threshold voltage fine tuning is achieved by the Vt adjust implants to the channel to affect the channel work function.
The gate dielectric or gate oxide is SiO2 or other dielectric interposed between the channel and the gate to electrically insulate the gate from the channel while allowing introduction of an electric field into the channel to control conduction between source and drain as a result of applying a voltage to the gate. MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate dielectric that is formed over the semiconductor surface. However, there are electrical and physical limitations on the extent to which SiO2 gate dielectrics can be made thinner. These include gate leakage currents tunneling through the thin gate oxide, difficulty of forming very thin oxide with uniform thickness, and dopant diffusion from the gate through thin gate dielectric into the underlying channel. For example, tunneling increases gate leakage and delivers into the channel, carriers of opposite type from the gate than the carriers intended in the channel which increases channel resistance and decreases on-current. Doping diffusion through gate dielectric produces threshold voltage Vt instability, channel mobility degradation and other problems.
One approach to provide equivalent gate capacitance and field effect performance uses high-k gate dielectric material having a dielectric constant greater than that of SiO2 and provided as a layer greater in thickness than a given thickness of the SiO2 by a ratio equal to the ratio of high-k dielectric constant to the dielectric constant of SiO2. (“k” refers to the dielectric constant of the dielectric material.)
Gate polysilicon depletion causes reduction in device performance which leads to poor unscalable devices. This poly depletion occurs when annealing or other thermal back-end processing of the implanted polysilicon is insufficient to drive the implanted impurities down the entire depth of the polysilicon gate structures or limited by dopant activation level in poly. A bottom portion of the polysilicon gate contact near the gate dielectric is “depleted” of charges, and acts as an insulator, increases the effective thickness between the effectively-acting gate and the channel and thereby reduces ability to control current flow in the channel. This is because part of the applied gate voltage is dropped across the gate itself. The electric field delivered to the channel by the gate is reduced at a given gate voltage, and the switching speed of the FET is reduced as a result.
Simply increasing the implant energy and/or anneal time to combat poly depletion has adverse results, in that the corresponding depths of the concurrently implanted source/drain regions are increased. Furthermore, because the implant process drives impurities to a variety of depths according to a statistical depth distribution, physical damage to gate dielectric occurs by impact and recoil. Moreover, alteration and damage not only occur to gate dielectric but also to the channel region by introduction of unintended impurities into both gate dielectric and channel region. As gates and gate dielectrics become thinner through scaling, the poly depletion region thickness becomes of proportionally greater significance relative to the effective gate thickness and relatively to the ever-thinner gate dielectric thickness. Polysilicon gate technology becomes less attractive as scaling efforts continue.
Metal gate technology in CMOS avoids polysilicon depletion issues with respect to gate capacitance, but there remains a need for dual or differentiated work function capability for the PMOS and NMOS transistors. Metal work functions are not shifted as easily as in polysilicon. Accordingly, there is a need for improved CMOS transistor designs and fabrication techniques by which the benefits of scaling can be achieved while avoiding or mitigating the poly depletion degradation found in conventional devices.
The references next described appear to involve various further problems in metal gate technology.
“Transistors with Dual Work Function Metal Gates by Single Full Silicidation (FUSI) of Polysilicon Gates” by W. Maszara et al. IEDM 2002: 367-370 describes a 1.7 nm (nanometer) equivalent oxide thickness nitride/oxide dielectric stack on SOI substrate and reports that polysilicon (poly) gates were doped with B (boron) and As (arsenic) for PMOS and NMOS. Additional gate spacers were reported to have been placed after deep s/d (source/drain) implants and before silicidation. Source/drain and gates were asserted to be fully silicided with nickel when 40 nm of nickel (Ni) was used. The authors say that the dopants, originally present in the polysilicon gates, have been segregated (“snow-ploughed”) in front of the advancing silicide front. The amount of piled-up arsenic at the top of gate dielectric is a significant fraction of ˜1 nm thick Ni—Si—As film, with over 50% of the implanted As does (4e15 cm-2) present in that pack, helping to modify the work function to ˜4.5 e.v. (electron volts) compared to pure NiSi reported to be 4.9 eV. Boron was less accumulated, and the reported PMOS work function of ˜4.9 e.v. was said to be apparently insufficient to modulate the NiSi work function.
However, among other problems, the silicidation if carried out over too long a time interval will damage the gate dielectric, and if performed over too short a time interval will not consume all the poly nor pile up sufficient dopant superjacent to the gate dielectric to modify a work function. Because of variations in real semiconductor device layers and the conditions of practical manufacturing processes, the critical and hard-to-control nature of this silicidation approach portends substantial manufacturing problems and yield uncertainties that translate into higher costs of technology solutions . Fully-silicided (FUSI) implementations have work function sensitivity to the silicide phase, metal diffusion into the oxide at high temperature, and material phase sensitivity to reaction/anneal temperature problems. The aforementioned problems and uncertainties can be expected to increase as workers consider how to address the challenges posed by sought-after processes with thinner layers of gate dielectric, narrower channel widths, and smaller gate dimensions.
U.S. Pat. No. 6,696,333 “Method of Making Integrated Circuit with MOSFETs Having Bi-Layer Metal Gate Electrodes” to Zheng et al. According to the patent, FIG. 4 suggests preparing a poly gate and spacers for PMOS and then removing the poly gate and then putting in a thin layer of tantalum nitride (TaN) metal formed over the surface of the partially completed integrated circuit, including over interior walls of sidewall spacers and over a gate dielectric layer. Then a second metal layer is formed over the TaN, said to typically be nickel, platinum, palladium, or other conductive material providing desirable work function. This is called gate replacement. Subsequently, an NMOS FET has its gate electrode such as silicide over poly removed down to substrate. Then a gate dielectric is put on, followed by a first layer of TiN (titanium nitride) 20 angstroms thick more or less. Then a second metal layer is formed, such as aluminum, titanium, or other conductive material with the desired work function. The reference says it is desirable that the TiN layer act as an effective barrier to diffusion of atoms from second metal layer into gate dielectric and also to overcome the carrier depletion effect at the gate/gate dielectric interface typically experienced with polysilicon gate electrodes (“poly depletion”).
However, this reference seems to require a very large number of steps to complete the gate replacements and various patterning, etching and layer formation steps to provide the various layers of differing materials for the complementary transistors successively and is believed to pose a risk of unavoidably damaging the underlying gate dielectric during poly gate removal or introducing further complication of removing and reforming the gate dielectric itself.
U.S. Pat. No. 6,373,111 says that P-channel FETS may include Pd/TiN (palladium-TiN) bi-layer. The TiN is called a work function modulation layer and different thicknesses are said to modify the work function, and consequently the threshold voltage of the transistor can be modified.
However, among other problems this reference would imply that multiple process steps would be needed to pattern, etch, and lay down the different work function modulation layers with either different materials or different thicknesses, or both, and such complications are believed to pose a risk of difficulty in thickness uniformity control across the wafer.
It is desirable for these problems and others to be ameliorated or solved in metal gate CMOS.